Terasic DE10-Standard FPGA 与 Quartus环境

DE10-Standard 是Intel FPGA University Program中的一款开发套件. 其核心部件为Altera的Intel System-on-Chip FPGA, 型号为Cyclone V 5CSXFC6D6F31C6;搭配了基于双核Cortex-A9嵌入式处理器的周边系统ARM-based hard processor system(HPS), 包含内存, 视频, 音频, 以太网等模块.

开发版照片

  • 正面照:
  • 背面照:
  • 系统结构框图:

开发板参数

  1. FPGA Device
    1. Cyclone V SX SoC—5CSXFC6D6F31C6N
    2. 110K LEs, 41509 ALMs
    3. 5,761 Kbits embedded memory
    4. 6 FPGA PLLs and 3 HPS PLLs
    5. 2 Hard Memory Controllers
  2. ARM-Based Hard Processor System (HPS)
    1. 925 MHz, Dual-Core ARM Cortex-A9 MPCore Processor
    2. 512 KB of Shared L2 Cache
    3. 64 KB of Scratch RAM
    4. Multiport SDRAM Controller with Support for DDR2, DDR3, LPDDR1, and LPDDR2
    5. 8-Channel Direct Memory Access (DMA) Controller
  3. Configuration and Debug
    1. Serial Configuration Device – EPCS128 on FPGA
    2. On-Board USB Blaster II (Normal Type B USB Connector)
  4. Memory Device
    1. 64MB (32Mx16) SDRAM on FPGA
    2. 1GB (2x256Mx16) DDR3 SDRAM on HPS
    3. MicroSD Card Socket on HPS
  5. Communication
    1. Two USB 2.0 Host Ports (ULPI Interface with USB Type A Connector) on HPS
    2. USB to UART (Micro USB Type B Connector) on HPS
    3. 10/100/1000 Ethernet on HPS
    4. PS/2 Mouse/Keyboard
    5. IR Emitter/Receiver
  6. Connectors
    1. One 40-pin Expansion Header (Voltage Levels: 3.3V)
    2. One HSMC Connector(Configurable I/O Standards 1.5/1.8/2.5/3.3V)
    3. One 10-Pin ADC Input Header
    4. One LTC Connector (One Serial Peripheral Interface (SPI) Master ,One I2C and One GPIO Interface ) on HPS
  7. Display
    1. 24-bit VGA DAC
    2. 128×64 Dots LCD Module with Backlight on HPS
  8. Audio
    1. 24-bit CODEC, Line-in, Line-out, and Microphone-In Jacks
    2. Video Input
    3. TV Decoder (NTSC/PAL/SECAM) and TV-In Connector
  9. ADC
    1. Sample Rate: 500 KSPS
    2. Channel Number: 8
    3. Resolution: 12 bits
    4. Analog Input Range : 0 ~ 4.096 V
  10. Switches, Buttons and Indicators
    1. 4 User Keys (FPGA x4)
    2. 10 User Switches (FPGA x10)
    3. 11 User LEDs (FPGA x10 ; HPS x 1)
    4. 2 HPS Reset Buttons (HPS_RST_n and HPS_WARM_RST_n)7-Segment Display x6
  11. Sensors
    1. G-Sensor on HPS
  12. Power
    1. 12V DC Input

引脚定义图

学习过程中会反复用到GPIO, 按键, 开关和LED, 下图展示了这些接口的引脚定义.

Quartus是与Altera FPGA配套的开发软件, 提供Lite, Standard, Pro三个版本, 其中Lite是免费的, 对于初学者是足够的.

安装Quartus Prime

  1. 从Intel的网站上下载此软件的Lite版本, 注意不一定最新版的就是最好的, 要与DE10-Standard相匹配!比如EP2C8Q208C8N是在Altera被Intel收购之前上市的产品, 最新的支持该FPGA的软件版本是13.0 sp1. Quartus Prime Lite Edition 传送门
  2. 下载之前需要注册一个Intel账户;
  3. 如下图所示, 选择Individual Files, 为了节省安装空间, 可以只选择Quartus Prime Lite Edition和Cyclone V device support 这个器件包:
  4. 安装过程按照程序提示安装即可, 遇到弹出提示安装驱动的窗口时单击“安装”即可.
  • de10_standard_and_quartus_intro.txt
  • Last modified: 3 months ago
  • by daizhirui